The real-time processing unit (RPU) in the processing system contains up to 10 core Cortex®-R52 real-time processor. Each of the Cortex-R52 cores has 32 KB of level 1 instruction and data cache with ECC protection. In addition to the L1 caches, each of the Cortex-R52 cores also has a 128 KB tightly-coupled memory (TCM) interface for real time single cycle access. To provide high-level safety, the Cortex-R52 cores are configurable as split-lock (split or lock-step). The cores are organized into independent, dual-core clusters.
The RPU communicates with the rest of the processing system via the low-power domain (LPD), non-coherent interconnect. The on-chip memory (OCM) is also connected to the LPD interconnect. OCM is organized into two banks of 2 MB (except for 2VM3654, it is 1 MB OCM). Each bank can be accessed through a dedicated 128-bit AXI interface via the LPD interconnect.
| Cortex-R5F | Cortex-R52 |
|---|---|
| Armv7-R architecture (32-bit operations) | Armv8-R architecture (64-bit and 32-bit operations) |
| Armv7 exceptions | EL0-EL3 exception levels |
| Vector Floating Point | Vector Floating Point |
| Up to 600 MHz | Up to 1050 MHz |
| 1.91 DMIPS per MHz per processor | 2.72 DMIPS per MHz per processor |
| 1 Dual-core Cluster (2 cores) | Up to 5 dual-core clusters (up to 10 cores) |
| 32 KB L1 instruction cache per processor | |
| 32 KB L1 data cache per processor | |
| 128K Tightly Coupled Memory (TCM) per processor | |
| Split Mode | |
| Dual Lock Step Mode | Dual Lock Step per cluster |