The Versal adaptive SoC programmable logic (PL) comprises configurable logic blocks (CLBs), internal memory, and DSP engines. Every CLB contains 64 flip-flops and 32 look-up tables (LUTs). Half of the CLB LUTs offer three configuration options. You can set them as a 64-bit RAM. They can function as either a single 32‑bit shift register (SRL32) or two 16‑bit shift registers (SRL16).
In addition to the LUTs and flip-flops, the CLB contains the following:
- Carry lookahead logic for implementing arithmetic functions or wide logic functions
- Dedicated, internal connections to create fast LUT cascades without external routing
This enables a flexible carry logic structure that allows a carry chain to start at any bit in the chain. In addition to the distributed RAM (64-bit each) capability in the CLB, there are dedicated blocks for optimally building memory arrays in the design:
- Accelerator RAM (4 MB)
- Available in some Versal devices only
- Block RAM (36 Kb each)
- Configure each port as 4Kx9, 2Kx18, 1Kx36, or 512x72 in simple dual-port mode
- UltraRAM (288 Kb each)
- Configure each port as 32Kx9, 16Kx18, 8Kx36, or 4Kx72
Versal devices also include many low-power DSP Engines, combining high speed with small size while retaining system design flexibility. Configure the DSP engines in various modes to better match the application needs. For example,
- 27×24-bit twos complement multiplier and a 58-bit accumulator
- Three element vector/INT8 dot product
- Complex 18bx18b multiplier
- Single precision floating point
For more information on PL resources, refer to the following documents: