Zynq UltraScale+ MPSoCs include power modes. These can map to Versal adaptive SoC power modes. Versal adaptive SoCs share peripherals that are power islands.
The PLM automatically turns off these power islands when not in use. Many main external power rails that supply power domains are currently supported for sleep states. Future releases will add additional support.
In Zynq UltraScale+ MPSoCs and Versal adaptive SoCs, PL power management methodology is similar and offers the largest power benefit. For more information, refer to this link in the Versal Adaptive SoC Board System Design Methodology Guide (UG1506).
In Versal adaptive SoC, the PMC error aggregation module (EAM) receives errors from the DDR, PL, SYSMON, and other system blocks. The PS management controller (PSM) routes PS errors to the EAM. Possible error actions are power-on reset (POR), system reset (SRST), error out, or interrupt software agents.
For detailed architectural differences, refer to the following documents: