The Versal architecture differs from previous architectures for boot and configuration. Versal adaptive SoC does not support the PL configuration and JTAG standalone primitives but similar capability exists as follows:
- Four JTAG TAP user instructions in the CIPS/PS Wizard IP replace the BSCANE2 primitive.
- The QSPI controller MIO and the CIPS/PS Wizard IP together replace the STARTUPE3 primitive. These include the global asynchronous set/reset, global 3-state, end of startup (EOS) signal, and PL clocks (PL0-PL3) source configuration.
- The JTAG DNA register or AXI memory mapped accessible 32-bit registers DNA_0, DNA_1, DNA_2, and DNA_3 replace the DNA_PORTE2 primitive. These registers enable reading the device DNA.
- The AXI memory mapped EFUSE_CACHE registers replace the EFUSE_USR primitive.
- The configuration frame interface (CFI) bus replaces the ICAPE3. You can access the CFI bus through the CIPS/PS Wizard IP.
- The PMC USR_ACCESS register in the PLM_RTCA (runtime configuration area) module replaces the USR_ACCESS primitive. For more information on PDI property setting, refer to the Vivado Design Suite User Guide: Programming and Debugging (UG908).
For more information on the memory mapped registers, including address mapping, refer to the following documents:
- Versal Adaptive SoC Technical Reference Manual (AM011)
- Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)
- Versal Adaptive SoC Register Reference (AM012)
- Versal AI Edge Series Gen 2 and Prime Series Gen 2 Register Reference with Security Registers (NDA version) (AM030), available under NDA from the Design Security Lounge