The Versal architecture differs from previous architectures for boot and configuration. Versal adaptive SoC does not support the PL configuration and JTAG standalone primitives but similar capability exists as follows:
- The BSCANE2 primitive is replaced by four JTAG TAP user instructions available in the CIPS/PS Wizard IP.
- The STARTUPE3 primitive is replaced by the combination of the QSPI controller MIO and CIPS/PS Wizard IP (global asynchronous set/reset signal, global 3-state, end of startup (EOS) signal, PL clocks (PL0-PL3) source configuration).
- The DNA_PORTE2 primitive is replaced by the JTAG DNA register or AXI memory mapped accessible 32-bit registers DNA_0, DNA_1, DNA_2, and DNA_3 to read out the device DNA.
- The EFUSE_USR primitive is replaced by the AXI memory mapped EFUSE_CACHE registers.
- The ICAPE3 is replaced by the configuration frame interface (CFI) bus, which is accessible through the CIPS/PS Wizard IP.
- The USR_ACCESS primitive is replaced by the PMC USR_ACCESS register in the PLM_RTCA (runtime configuration area) module. For more information on PDI property setting, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).
For more information on the memory mapped registers, including address mapping, see the Versal Adaptive SoC Technical Reference Manual (AM011) or Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026) and the Versal Adaptive SoC Register Reference (AM012).