PCIe Subsystems - PCIe Subsystems - 2026.1 English - UG1273

The Versal architecture includes several blocks for implementation of high-performance, standards-based interfaces built on PCI® -SIG technologies. In addition to the integrated CPM blocks, the Versal architecture includes support for implementation of PCIe® in the PL. PL PCIe are significantly enhanced implementations of the integrated blocks for PCIe found in previous architectures.

If your design needs to be migrated from an integrated block for PCIe in a previous architecture to a Versal adaptive SoC PL PCIe® block, consider the following:

• Currently, the Vivado IP integrator-based block design flow supports manual or automatic connectivity.
• The required GT and PHY IP blocks for Versal adaptive SoC PL PCIe are outside of the Versal adaptive SoC PL PCIe® block.
• Configure the PCIe subsystem with the required link speed, width, and features using the PL PCIe® block, and either run block automation or instantiate and connect the required GT and PHY IP manually.
• AMD recommends driving the fundamental reset for the PCIe controller using the I/O within the processing system. Configure it in the CIPS IP.
• Manually map RQ/RC/CQ/CC streaming interfaces and side band signals, which are similar to their respective IP implementation from previous architectures.

If your design must migrate from an integrated PCIe block in a previous architecture to a Versal architecture CPM block, consider the following points:

• Configure the PCIe subsystem with the required link speed, width, and features in the CPM using the CIPS IP core.
  Note: The CPM provides fixed connectivity to GTs based on its configuration. You cannot alter it. For guidance on GT selection and pin planning for CPM5, refer to this link in the Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347).
• The I/O inside the processing system drives the fundamental reset for the PCIe controller. Configure it in the CIPS IP.
• Only user_clk is available for the programmable logic. Its frequency is 62.5, 125, or 250 MHz depending on the configured link speed and width.
• Manually map RQ/RC/CQ/CC streaming, sideband signals, XDMA streaming, and QDMA streaming interfaces to Versal adaptive SoC CPM PL interfaces. These interfaces are similar to their respective IP implementation from previous architectures.
• Manually map the AXI4 memory-mapped (AXI4-MM) interfaces, including the AXI4-MM bridge, AMD DMA memory-mapped (XDMA-MM) interface, and Queue DMA memory-mapped (QDMA-MM) interface, into the NoC infrastructure. This requires setting up various components in the design, such as the NoC, processing system, address translation, and address allocation.

For more information, refer to the following documents for devices with CPM:

• Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)
• Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
• Versal Adaptive SoC PCIe PHY LogiCORE IP Product Guide (PG345)
• Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)
• Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)