The system automatically migrates block RAM and UltraRAM from previous architectures by inferring the appropriate Versal adaptive SoC block. The system also automatically migrates RTL instantiations. If the system does not support block RAM and UltraRAM configurations, it issues a critical warning message. It then converts to a black box element. You must change the design to adhere to the supported configurations for Versal adaptive SoC.
After migrating the design, AMD recommends that you examine the configuration settings to confirm the correct defaults and settings were automatically selected. AMD recommends using AMD parameterizable macros (XPMs) to infer FIFOs and other memories. Versal adaptive SoC does not support built-in FIFOs.
In the Vivado IP integrator, the Embedded Memory Generator and Embedded FIFO Generator replace the Block Memory Generator and FIFO Generator IP. The migration for the Block Memory Generator and FIFO Generator IP is not automatic. For detailed architectural differences, refer to the Versal Adaptive SoC Memory Resources Architecture Manual (AM007).
Some Versal adaptive SoCs include accelerator RAM (XRAM), an additional 4 MB of on-chip memory with ECC located adjacent to the PS. This memory provides direct access from the RPU via a 128-bit AXI interface. The PL can also access it through three 256-bit AXI interfaces. The system divides the memory into four banks that support concurrent read or write accesses from the PL and RPU. For details on the XRAM, refer to the Versal Adaptive SoC Technical Reference Manual (AM011).
Some Versal devices contain an array of AI Engine tiles on the north edge of the device. The AI Engine array is a two-dimensional array of AI Engine tiles that each contain:
- AI Engine
- High-performance VLIW vector (SIMD) processor
- Integrated data memory
- Interconnects for streaming, configuration, and debug
Within each AI Engine is a dedicated, single-port, 16 KB program memory 128-bit wide and 1k deep. The program memory supports instruction compression and has ECC protection and reporting.
Separate from the AI Engine, each AI Engine tile contains 32 KB of data memory for AI Engine and divided into eight single-port banks. For more details about RAMs dedicated to the AIE arrays, refer to the Versal Adaptive SoC AI Engine Architecture Manual (AM009).