The network on chip (NoC) is a high-speed communication subsystem. It transfers data between intellectual property (IP) Endpoints in the PL, PS, and other integrated blocks, providing unified intra-die connectivity. The NoC master and slave interfaces support configuration as AXI3, AXI4, or AXI4-Stream. The NoC converts these AXI interfaces to a 128-bit wide NoC packet protocol. The data moves horizontally and vertically across the device via the horizontal NoC (HNoC) and vertical NoC (VNoC), respectively.
The HNoC runs at the bottom and top of the Versal adaptive SoC. It is close to the I/O banks and integrated blocks (processors, memory controllers, and PCIe). The number of VNoCs (up to 8 VNoCs) depends on the device. It also depends on the amount of DDR memory controllers. For Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2, you can have up to 4 or 8 DDR memory controllers.
For Versal devices that use stacked silicon interconnect technology (SSIT), the NoC connects between the super logic regions (SLRs). It uses the NoC inter-die bridge (NIDB). For more information on the AXI protocol, refer to the Vivado Design Suite: AXI Reference Guide (UG1037).
Configure/program the NoC using the NoC programming interface (NPI). Perform this at early boot and before you use the NoC data paths. The NPI programs NoC registers that define the routing table, rate modulation, and QoS configuration. Programming of the NoC from the NPI normally requires no user intervention. Programming is fully automated and executed by the platform management controller (PMC)-embedded NPI controller.
For more information about boot and configuration, refer to the following documents:
- Versal Adaptive SoC Technical Reference Manual (AM011)
- Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)
The Versal adaptive SoC NoC IP acts as the logical representation of the Versal adaptive SoC NoC. The main function of the NoC is to efficiently move data between the DDR controllers and the rest of the device. The Versal adaptive SoC NoC IP enables multiple masters to access a shared DDR memory controller with advanced quality of service (QoS) settings.
Use the AXI NoC IP to connect the PS or the PL to the DDR memory controller. The AXI NoC IP allows for more connections. It links the PS to the PL. It also links design modules in the PL.
For more information on the NoC IP and performance, refer to the following documents: