Multiplexed I/O - Multiplexed I/O - 2026.1 English - UG1273

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2026-06-24
Version
2026.1 English

The Versal adaptive SoC multiplexed I/O (MIO) are similar to the MIO on the Zynq UltraScale+ MPSoCs. In Versal devices, there are 78 MIO pins. PMC MIO provides 52 signals in banks 500 and 501. LPD MIO provides 26 signals in bank 502.

For details on MIO pin planning, refer to this link and this link in the Versal Adaptive SoC Technical Reference Manual (AM011). For Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2, refer to the Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026). The CIPS/PS Wizard IP selects the MIOs to use and specifies their functionality.