The image signal processor (ISP) contains one to three ISP tiles for preprocessing raw image sensor data. Each ISP tile supports a maximum pixel rate of 600 megapixels per second with a maximum horizontal or vertical resolution of 4096 pixels. Linear and compressed formats support Input pixel depth.
ISP tiles are compatible with standard Bayer input (RGGB, GRBG, BGGR), monochrome (CCCC), RYYCy, RCCG, RCCC, and RGB-IR sensor types. An AXI4-Stream interface accepts streaming live data from a MIPI CSI-2 interface. ISP tiles also accept memory-input data from DMA read functionality and input test patterns from an in-built test pattern generator (TPG).
AXI4-Stream for live out and AXI4-memory mapped interfaces for memory out support the following video output formats:
- YUV 4:2:0
- YUV 4:2:2
- Y only
- 8 or 10 bits per component
- RGB888
Each ISP has dual output capability enabling primary output and secondary output with separate controls. One input stream can be processed by a single ISP tile for different primary and secondary output streams. RGB-IR image sensor data can be processed to provide RGB data on the primary output and IR data on the secondary output. In the memory out I/O type, both primary and secondary output DMA support raster half-DWORD aligned frame buffer format suitable for 10-bit max color depth.
For more information on the ISP, see the Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432).