High-Performance I/O - 2025.1 English - UG1273

The high-performance I/O in Versal adaptive SoC is known as XPIO or X5IO for Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2. The high-performance I/O are located at the bottom periphery of the device, unlike the columnar I/O architecture found in previous devices. High-performance I/O ports that exist below the processing system on the left side of the device and below the GTs on the right side of the device are known as corner I/O. Corner I/O have limited use, such as for the integrated DDR memory controller and limited clocking. For more information on XPIO, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010). For more information on corner I/O, see the Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).

The XPIO provide XPHY logic that is similar to AMD UltraScale™ device native mode. The XPHY logic encapsulates calibrated delays along with serialization and deserialization logic for six single-ended I/O ports known as nibble. Each XPIO bank contains nine XPHY logic sites and allows for up to 54 single-ended I/O ports. The XPHY logic is used for the integrated DDR memory controller, soft memory controllers, and any high-performance I/O interfaces.

For Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2, the X5IO provide X5IO PHY that is similar to AMD UltraScale™ device native mode. The X5IO PHY encapsulates calibrated delays along with serialization and deserialization logic for eight single-ended I/O ports known as octad. Each X5IO bank contains eight octad logic sites and allows for up to 64 single-ended I/O ports. The X5IO PHY is used for the integrated DDR memory controller, soft memory controllers, and any high-performance I/O interfaces.

Uncalibrated IDELAY, ODELAY, IDDR, and ODDR, known as I/O logic (IOL), exist in both XPIO and HD I/O banks to support legacy low-performance interfaces operating at 250 Mb/s and below.

The I/O planning flow for high-performance interfaces is different from previous architectures due to the use of XPHY/X5IO logic. If you previously generated high-performance interfaces using the AMD Memory Interface Generator, High-Speed SelectIO™ wizard, or SelectIO component mode, you must rebuild the interfaces using Versal IP wizards.

The following table shows how the high-performance UltraScale device I/O generation maps to the Versal device I/O generation.

After you regenerate the IP for the Versal adaptive SoC, you can perform I/O planning using the Advanced I/O Planner, which is similar to soft memory controller I/O planning flow for UltraScale devices. The Advanced I/O Planner guides you through the process of mapping your interfaces to the desired XPIO/X5IO banks using the XPHY/X5IO logic, ensuring that your high-speed interfaces are legally mapped to the XPHY/X5IO logic.

AMD recommends I/O planning high-speed interfaces in the following order to achieve the maximum utilization of available XPHY/X5IO logic resources:

1. Integrated DDR memory controller via NoC
2. Soft memory controllers
3. Advanced I/O Wizard
4. X5IO Wizard
5. I/O logic

For information, see the following documents:

• For DDR4 and LPDDR4 pinout rules, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).
• For DDR5 and LPDDR5/5X pinout rules, see the Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406) and Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456).
• For soft memory controller rules, see the Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353) and Versal Adaptive SoC Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354) .
• For information on the Advanced I/O wizard, see the Advanced I/O Wizard LogiCORE IP Product Guide (PG320).