The Vitis design flow implements and deploys the same subsystem on hardware. You can also simulate this subsystem using the hardware emulation flow. When targeting a hardware board, the Vitis linker sends the PL region of the system through Vivado synthesis as well as place and route.
By testing in hardware, you can get early feedback on timing closure and resource utilization. Most importantly, you can run the subsystem at speed on hardware for more realistic performance results as follows:
- More accurate execution profile of control code running on the PS
- More realistic I/O patterns, resulting in more realistic exercising of stalls and back pressure
- Slower hardware emulation runs cannot reach certain corner cases
Using a combination of compile-time and runtime options, the Vitis environment design flow allows you to select which information to profile or trace. When running on the hardware board, the system collects information automatically, and is viewable with the Vitis Analyzer tool.
For more information on how to assemble and verify the subsystem on hardware, refer to the Implementation and System Bring Up and Validation sections of the Versal Adaptive SoC Design Process Hubs: System Integration and Validation.