The heterogeneous nature and performance of the Versal adaptive SoC requires a system-level high-bandwidth debug and trace solution. The high-speed debug port (HSDP) is a new Versal adaptive SoC feature. It provides unified, at-speed debugging and tracing for integrated, fabric-based, and processor blocks in the device under test (DUT). HSDP provides the option to perform debug and trace capture through a dedicated Aurora interface and a high‑speed debug cable such as SmartLynq+.
Remote systems connected to a host through PCIe can also use high-speed debug over PCIe. High-speed GT‑based interfaces provide access to HSDP functions. These include the integrated Aurora interface in the PS block or the PCIe interface in the CPM block.
For more information, refer to the following resources:
- This link in the Versal Adaptive SoC Technical Reference Manual (AM011)
- Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)
- SmartLynq+ Module User Guide (UG1514)
- System Design Example for High-Speed Debug Port (HSDP) with SmartLynq+ Module