The Versal high-bandwidth memory (HBM) controller provides access to one or two stacks depending on the selected device:
- Up to 128 Gb (16 GB) for four high stacked devices
- Up to 256 Gb (32 GB) for eight high stacked devices
Eight independent HBM controllers connect to a single stack. Each of the HBM controller supports two mostly independent pseudo channels, each addressing a dedicated segment of HBM. Each pseudo channel has a 64-bit wide data bus with a shared command/address/control (CAC) bus. The total data-bit width of an HBM stack is 1,024 bits divided across 16 pseudo channels.
The controller and PHY operate at up to 1,600 MHz for a data transfer rate of 3,200 MT/s. With 128 bits per HBM controller, eight controllers per stack, and two stacks in most devices, this yields a maximum throughput of 819 GB/s.
The HBM controller interfaces to user logic in PL via the NoC. Each pseudo channel has a dedicated pair of NoC slave ports. Each quad of HBM pseudo channels receives an 8x8 switch. The NoC combined with the switches allow global addressing to the entire HBM stack from any master connected to the NoC. You can configure the NoC IP core to include a subset or all the integrated HBM controllers.
For information on the HBM controller, refer to the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).