For Versal adaptive SoC, GT components are updated from Common/Channel to a GT Quad granularity. To enable some of the GT sharing use cases, GT wizard flows are modified to use the Vivado IP integrator. Use the Vivado IP integrator to build system designs that use single or multiple GT Quads. The design entry for custom IP connects to GT Quads via the Bridge IP, which instantiates, configures, and connects single or multiple GT Quad-based IP through Block Automation. For more information, see the Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).
In addition to the Transceivers Wizard, AMD also provides the Versal adaptive SoC Transceiver Subsystem IP, which offers a higher-level, more integrated approach to transceiver implementation. While the Transceivers Wizard provides low-level access to GT primitives for custom protocol development, the Transceiver Subsystem IP includes pre-configured protocol stacks, integrated clocking and reset management, and system-level connectivity features that simplify implementation of standard protocols like PCIe and Ethernet. For most users implementing standard protocols or requiring system-level integration, the Transceiver Subsystem is the recommended starting point. For detailed information about the Transceiver Subsystem IP, see the Versal Adaptive SoC Transceiver Subsystem Product Guide (PG442).
When migrating your design to the Versal device, consider using the Transceiver Subsystem IP for standard protocols as it provides a more streamlined migration path with built-in system integration features. However, you must be aware of the full GT Quad layout and supported configuration options regardless of which IP you choose. For detailed architectural differences, see the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) and Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017).