Certain PMC and LPD peripherals are routed via the extended multiplexed I/O (EMIO) interface through the PL to XPIO/X5IO or HD I/O via I/O logic. For details on which peripherals can access the EMIO, see this link in the Versal Adaptive SoC Technical Reference Manual (AM011). For Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2, see the Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026). On the CIPS/PS Wizard IP, use the IO Configuration page to select EMIO peripherals. EMIO uses I/O logic. EMIO pin planning is done using the traditional drag-and-drop pin planning in the Vivado Design Suite.
Power Tip: When pin planning the EMIO in
the XPIO or HD I/O, consider the I/O voltage requirements of the peripheral interface in
choosing the bank type. XPIO banks can support I/O voltages of 1.5V and below while HD
I/O banks can support I/O voltages of 1.8V and above. For XPIO banks, the recommendation
is to place the lower-speed I/O logic last to maximize package pin utilization. This can
leave a limited selection of I/O standards based on previously assigned I/O. You must
ensure that your interface is feasible in the desired bank or banks. You can use the
IBIS models to simulate the interface at your required speed with the I/O standard
selected for your bank.