When migrating from UltraScale/UltraScale+ devices using Integrated 100G Ethernet (CMAC) hard blocks or soft 10G/25G/40G or 50G Ethernet IP, consider the following items.
- MRMAC provides wider customization for line rate, clocking, and user
interface:
- Supported configurations are: 1 x 100GE, 2 x 50GE, 1 x 40GE; 4 x 25GE, and 4 x 10GE.
- MRMAC now has an integrated AXIS interface for MAC+PCS operation as opposed to CMAC, which offered integrated 512-bit LBUS interface with optional AXIS interface.
- Various AXIS bus widths and clocking options are available. The options depend on the configuration. They can vary from those in UltraScale or UltraScale+ device CMAC or soft core solutions.
- There is a new Flex Port option for access to PCS level.
- MRMAC core does not include the GT. An IP integrator block automation connects the MRMAC and GT.
- The design integrates the statistics registers into the hard block instead of providing statistic counter increment vectors. They are available over AXI4-Lite.
- The MRMAC also supports a new high-precision timestamping feature to enable sub-nanosecond accuracy on IEEE Std 1588 timestamps.
For MRMAC information and example design generation details, refer to the Versal Devices Integrated 100G Multirate Ethernet MAC (MRMAC) LogiCORE IP Product Guide (PG314).