RTL kernels and the Vivado Design Suite can also be used to develop PL kernels. This approach is convenient for hardware engineers that have existing RTL IP, including Vivado IP integrator-based designs, or prefer creating new functions by writing RTL code.
An RTL kernel is a regular design packaged as Vivado Design Suite IP. The kernel must comply with specific interface rules and requirements to be usable in the Vitis environment design flow. For more information about RTL kernels, see this link in the Data Center Acceleration using Vitis (UG1700).
Creating an RTL kernel follows traditional RTL design guidelines. AMD recommends dedicated test benches. Use behavioral simulation to thoroughly verify the RTL code before packaging and using the code as PL kernels in the Vitis environment design flow. After an RTL design is fully verified and meets all the requirements for a Vitis kernel, the Vivado IP packager can be used to package the design in a Vitis kernel object (XO file).
For more information on how to develop and simulate RTL kernels, see the Create PL Kernels Using RTL section of the Versal Adaptive SoC Design Process Documentation: Hardware, IP, and Platform Development Guided - Platform.