Developing PL Kernels with RTL and the Vivado Design Suite - Developing PL Kernels with RTL and the Vivado Design Suite - 2026.1 English - UG1273

Use RTL kernels and the Vivado Design Suite to develop PL kernels. This approach suits hardware engineers with existing RTL IP, including Vivado IP integrator-based designs, or those who prefer creating new functions in RTL.

An RTL kernel is a regular design packaged as Vivado Design Suite IP. The kernel must comply with specific interface rules and requirements to be usable in the Vitis environment design flow. For more information about RTL kernels, refer to this link in the Data Center Acceleration using Vitis (UG1700).

Creating an RTL kernel follows traditional RTL design guidelines. AMD recommends dedicated test benches. Use behavioral simulation to thoroughly verify the RTL code before packaging and using the code as PL kernels in the Vitis environment design flow. After you complete RTL design verification and meet the requirements, use Vivado IP packager to create a Vitis kernel object (XO file).

For more information on how to develop and simulate RTL kernels, refer to the Guided - Platform Based > Create PL Kernels Using RTL of the Versal Adaptive SoC Design Process Hubs: Hardware, IP, and Platform Development Guided - Platform Based.