The Versal architecture introduces new hardware features that require additional considerations to reach design closure, including timing and performance closure. Similarly to previous AMD device architectures, the timing summary report is the signoff report for timing closure. Vivado Design Suite compilation tools provide guidance with the following reports:
- Design rule checks (DRCs) prevent invalid hardware configurations (
report_drc). DRC violations with severity level of Critical Warning and Error prevent the device image file generation and must be addressed. - Methodology checks improve the PL maximum operating frequency and identify
common unsafe design structures, which can lead to hardware malfunction or
instability (
report_methodology,report_cdc). Address critical and warning violations to help timing closure and hardware stability. - AMD also recommends addressing critical warnings in the log file.
Important: To reduce timing closure
iterations, review and address the timing violations as early as possible in the
implementation flow, especially after synthesis and after physical optimization.
Due to the heterogeneous nature of the Versal architecture, the design performance mostly depends on the following:
- NoC QoS
- DDR memory access
- Software efficiency in PS and AI Engines
- PL operating frequency
- Amount of pipelining
For information on timing, system performance, and power design closure, see the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).