Design Address Map - Design Address Map - 2026.1 English - UG1273

The Versal adaptive SoC uses a single, unified system address map. All memory-mapped AXI transactions must adhere to this map. The Versal adaptive SoC system address map defines the default address locations of slaves in the Versal adaptive SoC.

The PL-based SmartConnect and the NoC include the address map. The Vivado IP integrator automatically resolves the base name, offset address, and the address region range. It bases them on the DDR4 memory options selected in the AXI NoC IP customization.

The AXI master uses these addresses to communicate with the DDR. Use the Vivado IP integrator Address Editor to select or automatically assign compliant addresses for all the memory-mapped blocks within the design.

For NoC and related IP configuration, and system address map details, refer to the following documents:

• Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)
• Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406)
• Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)