DDR Memory Controller for DDR5, LPDDR5, and LPDDR5X - DDR Memory Controller for DDR5, LPDDR5, and LPDDR5X - 2026.1 English

DDR Memory Controller for DDR5, LPDDR5, and LPDDR5X - DDR Memory Controller for DDR5, LPDDR5, and LPDDR5X - 2026.1 English - UG1273

Versal Adaptive SoC Design Guide (UG1273)

Document ID

UG1273

Release Date

2026-06-24

Version

2026.1 English

Note: This section provides guidelines for the Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2.

The DDR5/LPDDR5/5X memory controller is a high-efficiency, low-latency integrated memory controller for various applications.

The controller operates at half the DRAM clock frequency and supports DDR5, LPDDR5, and LPDDR5X standards up to 8,533 Mb/s. The controller can be configured as a single DDR memory interface with data widths up to 32 bits. The system also supports dual channel configurations with data widths up to 16 bits.

The controller supports both sideband and in-line error correction code (ECC) configurations. The controller supports DDR5 and LPDDR5/5X components, and DDR5 dual in-line memory modules (DIMMs). The memory controller includes optional AES-GCM or AES-XTS encryption. AES-GCM encryption includes a built-in side channel leakage reduction feature to provide resistance to dynamic power analysis (DPA) or side channel analysis (SCA).

Important: There are multiple variants of the memory controller. The maximum interface rates and supported features and configurations vary between versions.

For more information on the memory controller, refer to the Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456).