This section describes the Arm® Cortex®-A72-based processing system in the Versal AI Edge Series, Versal AI Core Series, Versal Prime Series, and Versal Premium Series.
Note: The Arm
Cortex-A78AE-based processing system in the Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 is described in the Processing System Wizard.
Important: The CIPS IP is
applicable to most devices with the Arm
Cortex-A72-based processing system. The relevant families are Versal AI Edge Series, Versal AI Core Series, Versal Prime Series,
Versal Premium Series, and Versal RF Series.
The VP1902, VM2152, and Versal RF devices have an Arm Cortex-A72-based processing system, but use the PS Wizard IP rather than the CIPS IP.
The PS, PMC, and CPM modules are grouped together and configured using the Control, Interface, and Processing System (CIPS) IP core as shown in the following figure.
Note: The Versal adaptive SoC includes multiple power domains. In the PS, the RPU
is in the low-power domain (LPD), the APU is in the full-power domain (FPD), and the
platform management controller (PMC) is in the PMC power domain. CPM has two
implementations depending on the target device capability:
- CPM4 that is compliant with the PCI Express Base Specification Revision 4.0
- CPM5 that is compliant with the PCI Express Base Specification Revision 5.0
Figure 1. Device-Level Interconnect Architecture
