The Control, Interfaces, and Processing System (CIPS) Verification Intellectual Property (VIP) or Processing Systems (PS) VIP supports the functional simulation of Versal adaptive SoC applications. This design enables functional verification of programmable logic (PL) by mimicking the processor system (PS)-PL interfaces and OCM memories of PS logic. This VIP is delivered as a package of SystemVerilog modules. A sequence of SystemVerilog tasks controls the VIP operation. For more information, refer to the Versal Adaptive SoC CIPS Verification IP Data Sheet (DS996) or Versal Adaptive SoC Processing Systems Verification IP (DS1045).