Block RAM Primitives - Block RAM Primitives - 2026.1 English - UG1273

Following are the block RAM primitives in Versal adaptive SoC.

In SDP mode, one address reads the RAM and the other address writes to the RAM. You can use different clocks for the read and the write, but the address lines must be separate. The following figures show examples.

Figure 1. Verilog Coding Style for a 512x72 Block RAM in SDP Mode

Figure 2. VHDL Coding Style for a 512x72 Block RAM in SDP Mode

Resets

Following are the types of resets on the block RAM:

• Synchronous reset on the block RAM output, which uses the RESETRAMA or RESETRAMB pin
• Asynchronous reset on the block RAM output, which uses the ARST_A or ARST_B pin
  Note: Using ARST_A/B pin ignores the RESETRAMA, RESETRAMB, RSTREGA, and RSTREGB pins.
• Synchronous reset that controls the optional output registers of the block RAM, which uses the RSTREGA or RSTREGB pin

When using asynchronous resets, see the following guidelines:

• Both the RAM and optional output register must use the same asynchronous reset.
  Note: If the optional output register does not use the same reset, the register does not infer into the block RAM.
• The output enables. The design ignores the SRVAL properties.
• The asynchronous reset can only reset to a 0 value.

Write Modes

The Versal adaptive SoC block RAMs support the same write modes as AMD UltraScale™ devices and use the same RTL coding styles:

• WRITE_FIRST outputs the newly written data onto the output bus.
• READ_FIRST outputs the previously stored data onto the output bus.
• NO_CHANGE maintains the previous value of the output bus.

Byte Write Enables

The control ports for byte write enables are the WEA and WEB pins, which vary based on usage:

• RAMB36E5
  • In non-SDP mode, the WEA and WEB [3:0] pins control 4 bytes of either size 8 or 9.
  • In SDP mode, the WEA and WEB [7:0] pins control 8 bytes of size 8 or 9.
• RAMB18E5
  • In non-SDP mode, the WEA and WEB [1:0] pins control 2 bytes of size 8 or 9.
  • In SDP mode, pins WEA and WEB [3:0] pins control 4 bytes of 8 or 9.

Currently, Vivado synthesis infers byte write RAM for sizes of 8 or 9. In addition, Vivado synthesis only infers byte write enable RAM if the enables use one-hot state encoding.

For example, consider a byte write enabled RAM. It is configured as true dual port with a data width of 36. This RAM has four different bytes, but you can write only 1 byte at a time. To infer the block RAM, ensure the RTL adheres to these restrictions.

Asymmetric RAMs

For asymmetric block RAMs in Versal adaptive SoCs, use the same coding styles and rules that you use for asymmetric block RAMs in UltraScale devices. For information on setting up asymmetric block RAMs, refer to the Vivado Design Suite User Guide: Synthesis (UG901).

Using XPMs

XPMs can also infer block RAMs. The advantage of using this approach is that XPMs always have the correct coding style for any type of RAM needed. For more information on XPMs, refer to the Vivado Design Suite User Guide: System-Level Design Entry (UG895).