Several migration paths exist for the soft AXI Interconnect IP. The two most common paths are the AXI Switch IP for RTL centric designs or the SmartConnect IP for Vivado IP integrator based designs. Alternatively, Versal devices provide a hardened NoC that supports AXI interconnect. Prioritize NoC resources first for high-bandwidth connections to the integrated DDR memory controllers. After you account for these connections, use the remaining NoC bandwidth to reduce PL resource utilization. Shift the AXI interconnect from the PL resources to hardened NoC resources.
Vivado enables two flows to assist with migrating AXI Interconnect to the Versal NoC. The modular NoC flow integrates well with RTL-centric designs. It uses NoC Xilinx parameterized macros (XPMs) to connect RTL AXI interconnect to the hardened NoC resources.
For Vivado IP Integrator designs, place the AXI NoC IP on the block design canvas to access the NoC. In addition, the AXI NoC IP is the only way to incorporate the Versal hardened memory controllers into your design. You can use these flows simultaneously in the same design.
For more information on the IP and the stated flows, refer to the following documents:
- Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)
- Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406)
- Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
- SmartConnect LogiCORE IP Product Guide (PG247)
- AXI Switch LogiCORE IP Product Guide (PG453)
- Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)