Several migration paths exist for the soft AXI Interconnect IP. The two most common paths are the AXI Switch IP for RTL centric designs or the SmartConnect IP for Vivado IP integrator based designs. Alternatively, Versal devices provide a hardened NoC that can be used for AXI interconnect. NoC resources should first be prioritized for high-bandwidth connections to the integrated DDR memory controllers. After these connections are accounted for, the remaining NoC bandwidth can be used to reduce PL resource utilization by shifting AXI interconnect from the PL resources to the hardened NoC resources.
Two flows are enabled in Vivado to assist with migrating AXI Interconnect to the Versal NoC. The modular NoC flow integrates well with RTL centric designs by using NoC Xilinx parameterized macros (XPMs) to connect RTL AXI interconnect to the hardened NoC resources. For Vivado IP integrator designs, the NoC is accessed by placing the AXI NoC IP onto the block design canvas. In addition, the AXI NoC IP is the only way to incorporate the Versal hardened memory controllers into your design. These flows can be used simultaneously in the same design. For more information on the IP and the stated flows, see the following documents:
- Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)
- Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406)
- Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
- SmartConnect LogiCORE IP Product Guide (PG247)
- AXI Switch LogiCORE IP Product Guide (PG453)
- Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)