The PS-PL Arm Advanced Microcontroller Bus Architecture (AMBA) specification interfaces in the Versal adaptive SoC. They have similar functionality to Zynq UltraScale+ MPSoCs. Refer to the following table.
Note: Enabling and
disabling the different power domains in the LPD, FPD, and PL enables and
disables the AXI connections to those domains.
Important: The DDR memory controller
shares the PS and PL. It does this via the device-wide, high-performance NoC
interface. This sharing results in fewer PS-PL AXI interconnects.
| PS-PL AMBA Interface | Master | Coherency | Zynq UltraScale+ MPSoC | Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 | ||
|---|---|---|---|---|---|---|
| Name | Count | Name | Count | |||
| Accelerator Coherency Port (ACP) | PL | I/O | S_AXI_ACP_FPD | 1 | PL_ACP_APU | 1 |
| AXI Coherency Extensions (ACE) | PL | 2-way | S_AXI_ACE_FPD | 1 | - | - |
| Coherent Hub Interface (CHI) | PL | 2-way | - | - | PL_CHI_FPD | 1 |
| PL-to-FPD AXI | PL | - | S_AXI_HPx_FPD | 4 | FPD_AXI_PL | 1 |
| PL-to-FPD AXI | PL | I/O | S_AXI_HPCx_FPD | 2 | PL_ACELITE_FPDx | 4 |
| PL-to-LPD AXI | PL | - | S_AXI_LPD | 1 | PL_AXI_LPD | 1 |
| FPD-to-PL AXI | FPD | - | M_AXI_HPMx_FPD | 2 | FPD_AXI_PL | 1 |
| LPD-to-PL AXI | LPD | - | M_AXI_HPM0_LPD | 1 | LPD_AXI_PL | 1 |