Instantiate the AI Engine IP and connect it to the rest of the design. This generates an extensible platform for the Vitis environment. A base platform hardware design includes a minimally configured AI Engine IP block. The system enables any memory-mapped slave AXI connections. They connect to the dedicated NoC bus masters.
All other AI Engine configurations occur through compilation of the user ADF graph and AI Engine kernels. The Vitis aiecompiler and Vitis v++ linking configure the AI Engine by linking the aiecompiler libadf.a with the extensible platform design. AI Engine connects to the base platform. It uses AXI4-Stream master and slave connections, memory-mapped AXI bus connections to NoC, and clocks for the bus interfaces. The IP triggers AI Engine events, then transfers them to memory and to XSDB through the AXI4 connections.
For more information, refer to the following documents: