[This Figure, callout 9]
The QSFP1 clock source is a Silicon Labs SI5335A quad clock generator/buffer (U48).
•Clock generator: Silicon Labs SI5335A-B06201-GM (CLK0A 300 MHz)
°Frequency plan: FS1, FS0=01
-Input type: crystal, input frequency 25 MHz
-Device operating mode: clock generator loop bandwidth 1.6 MHz
-CLK0A/0B: 300 MHz 1.8V LVDS
-CLK1A/1B: 156.25 MHz 1.8V LVDS
-CLK2A/2B: 90 MHz 1.8V CMOS (output on A only)
-CLK3A/3B: 33.333 MHz 1.8V CMOS (output on A only)
•Low phase jitter of 0.7pS RMS
One output of the SI5335A U48 is used:
•CLK0A/B are not used.
•CLK1A/B
The QSFP1_CLOCK_P/N clock is an AC coupled LVDS 156.25 MHz clock wired to QSFP1 interface MGTH bank 128 MGTREFCLK1P/N input pins AN36 and AN37.
•CLK2A is not used.
•CLK3A is not used.
The QSFP1 clock circuit is shown in This Figure.
