Programmable MGT and User Clock

KCU1500 Board User Guide (UG1260)

Document ID
Release Date
1.5 English

[This Figure, callout 10]

The KCU1500 board has a SI570 programmable low-jitter 3.3V LVDS differential oscillator (U40) connected to a SI53340 (U41) 1-to-4 LVDS clock buffer.

On power-up, the SI570 user clock defaults to an output frequency of 156.250 MHz. User applications can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the KCU1500 board resets this clock to the default frequency of 156.250 MHz.

Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz–810 MHz)

Frequency jitter: 50 ppm

3.3V LVDS differential output

Default frequency 156.250 MHz

Three of the SI53340 (U41) 1-to-4 LVDS clock buffer outputs are used:


USER_SI570_CLOCK_P/N are wired to QSFP0/1 control I/O bank 84 GC input pins. The I2C_MAIN_SDA/SCL bus is also wired to bank 84.

Q1_P/N are not used.


MGT_SI570_CLOCK0_P/N are AC coupled to MGTH bank 127.


MGT_SI570_CLOCK1_P/N are AC coupled to MGTH bank 128.

The QSFP1 clock circuit is shown in This Figure.

Figure 3-4:      SI570 Clock Circuit

X-Ref Target - Figure 3-4