PCI Express Endpoint Connectivity

KCU1500 Board User Guide (UG1260)

Document ID
Release Date
1.5 English

[This Figure, PCIe Edge Connector]

The 16-lane PCI Express® edge connector CN1 performs data transfers at the rate of 2.5 GT/s for Gen1 applications, 5.0 GT/s for Gen2 applications, and 8.0 GT/s for Gen3 applications. The PCIe transmit and receive signal data paths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair.

The XCKU115-2FLVB2104E device (–2 speed grade) included with the KCU1500 board supports up to Gen3 x16 bifurcated into two Gen3 x8 channels.

The PCIe clock is input from the CN1 edge connector and AC coupled to a 1-to-2 SI53322 clock buffer. The clock buffer outputs are AC coupled to FPGA U1 MGTREFCLK0 pins of Quad 225 and 226 to support two x8 bifurcated channels (also see This Figure).

The PCI Express clock circuit is shown in This Figure.

Figure 3-6:      PCI Express Clock Buffer

X-Ref Target - Figure 3-6