[This Figure, callout 1]
The KCU1500 board provides access to 24 of the 64 GTH transceivers:
•Four GTH transceivers (bank 127) are wired to QSFP28 connector QSFP0 J28
•Four GTH transceivers (bank 128) are wired to QSFP28 connector QSFP1 J30
Sixteen GTH transceivers are wired to the PCIe edge connector PEX signals:
•Four GTH transceivers (bank 224) are wired to PCIe edge connector CN1 lanes 7:4
•Four GTH transceivers (bank 225) are wired to PCIe edge connector CN1 lanes 3:0
•Four GTH transceivers (bank 226) are wired to PCIe edge connector CN1 lanes 15:12
•Four GTH transceivers (bank 227) are wired to PCIe edge connector CN1 lanes 11:8
The GTH transceivers in the XCKU115 device are grouped into four channels or quads. The reference clock for a quad can be sourced from the quad above or the quad below the GTH quad of interest. The six GTH quads used on the KCU1500 board have the connectivity listed here (also see This Figure):
Quad 127:
•MGTREFCLK0 – MGT_SI570_CLOCK0_C_P/N
•MGTREFCLK1 – QSFP0_CLOCK_P/N
•Contains four GTH transceivers allocated to QSFP0 TX/RX lanes 1–4
Quad 128:
•MGTREFCLK0 – MGT_SI570_CLOCK1_C_P/N
•MGTREFCLK1 – QSFP1_CLOCK_P/N
•Contains four GTH transceivers allocated to QSFP1 TX/RX lanes 1–4
Quad 224:
•MGTREFCLK0 – not connected
•MGTREFCLK1 – not connected
•Contains four GTH transceivers allocated to PCIe lanes 7–4
Quad 225:
•MGTREFCLK0 – PEX_REFCLK_225_P/N buffered PCIe edge connector clock
•MGTREFCLK1 – not connected
•Contains four GTH transceivers allocated to PCIe lanes 3–0
Quad 226:
•MGTREFCLK0 – PEX_REFCLK_226_P/N buffered PCIe edge connector clock
•MGTREFCLK1 – not connected
•Contains four GTH transceivers allocated to PCIe lanes 15–12
Quad 227:
•MGTREFCLK0 – not connected
•MGTREFCLK1 – not connected
•Contains four GTH transceivers allocated to PCIe lanes 11–8
