FPGA Configuration

The KCU1500 board supports two AMD UltraScale™ FPGA configuration modes:

•Quad SPI flash memory

•JTAG using:

°Platform cable header J2

°USB JTAG configuration port (USB J34/FT2232H U65)

At power up, the FPGA is configured by dual Quad SPI NOR flash devices (Micron MT25QU512ABB8E12-0SIT) operating at a clock rate of 90 MHz (EMCCLK) using the "Master SPI" Configuration mode. An external EMCCLK configuration clock is used to allow for the highest configuration speed with SPI flash, and the dual Quad SPI flash memory devices provide a total datapath of 8 bits.

Each of the Quad SPI flash memory NOR devices has a capacity of 512 Mb. The two Quad SPI flash memory devices provide a combined configuration capacity of 1 Gb.

Two configuration modes are supported on the KCU1500, as listed in Table: Configuration Modes. While the FPGA mode pins M2, M1, and M0 are wired to the active-Low mode DIP SW5, only M2 on SW5 pin 7 should be toggled to select between M[2:0] = 001 and 101. The FPGA default mode setting is M[2:0] = 001 = SW5[2:4] = (On, On, Off), selecting the Quad SPI flash memory configuration mode.

For complete details on configuring the FPGA, see the UltraScale Architecture Configuration User Guide (UG570) [Ref 1].

The mode DIP SW5 is shown in This Figure.

Note:   For this DIP SW5 switch, moving the switch toward the label ON is a 0. DIP switch labels 2, 3, and 4 are equivalent to mode pins M2, M1, and M0. The default = master SPI = M[2:0] = 001 = SW5[2:4] = On, On, Off.