Clock Generation

KCU1500 Board User Guide (UG1260)

Document ID
UG1260
Release Date
2023-07-27
Revision
1.5 English

[This Figure, callout 9, 10]

The KCU1500 board provides eight clock sources to the XCKU115 device as listed in Table: KCU1500 Board Clock Sources.

Table 3-2:      KCU1500 Board Clock Sources

Clock Name  

 Clock Ref. Des.  

Description

System clock 300 MHz

 U47 (CLK0)  

Silicon Labs Si5335A 1.8V LVDS any frequency quad clock generator CLK0. See System Clock, QSFP0 Clock, and EMCCLK (SYSCLK_300_P/N).

 QSFP0 clock 156.25 MHz

U47 (CLK1)

Silicon Labs Si5335A 1.8V LVDS any frequency quad clock generator CLK1. See System Clock, QSFP0 Clock, and EMCCLK (QSFP0_CLOCK_P/N).

 EMC clock 90 MHz

U47 (CLK2)

Silicon Labs Si5335A 1.8V LVCMOS single-ended any frequency quad clock generator CLK2. See System Clock, QSFP0 Clock, and EMCCLK (FPGA_EMCCLK).

 QSFP1 clock 156.25 MHz

U48 (CLK1)

Silicon Labs Si5335A 1.8V LVDS any frequency quad clock generator CLK1. See QSFP1 Clock (QSFP1_CLOCK_P/N).

User MGT clock 10 MHz–810 MHz

U40

Silicon Labs Si570 3.3V LVDS I2C programmable oscillator, 156.250 MHz default. (USER_SI570_CLOCK_P/N and USER_MGT_SI570_CLOCK[1:0]_P/N). See Programmable MGT and User Clock.

PEX_REFCLK (PCIe® input)

CN1/U55

PCIe edge connector. CN1 input clock 100 MHz to SI53322 U55 1-to-2 clock buffer (PEX_REFCLK_225/226_P/N).