Zynq UltraScale+ MPSoC System Configuration with Vivado - 2024.2 English - UG1209

Zynq UltraScale+ MPSoC Embedded Design Tutorial (UG1209)

Document ID
UG1209
Release Date
2025-01-07
Version
2024.2 English

This chapter demonstrates how to use the Vivado® Design Suite to develop an embedded system using the Zynq® UltraScale+™ MPSoC Processing System (PS).

The Zynq UltraScale+ device consists of quad-core Arm® Cortex™-A53-based APU, dual-core Arm® Cortex™-R5F RPU, Mali™ 400 MP2 GPU, many hard Intellectual Property (IP) components, and Programmable Logic (PL). This offering can be used in two ways:

  • The Zynq UltraScale+ PS can be used in a standalone mode, without attaching any additional fabric IP.

  • IP cores can be instantiated in fabric and attached to the Zynq UltraScale+ PS as a PS+PL combination.