Managing the Zynq UltraScale+ Processing System in Vivado - 2024.2 English - UG1209

Now that you have added the processing system for the Zynq MPSoC to the design, you can begin managing the available options.

1. Double-click the Zynq UltraScale+ Processing System block in the Block Diagram window.

   The Re-customize IP view opens, as shown in the following figure. Notice that by default, the processor system does not have any peripherals connected.

   

2. Click Cancel to exit the view without making changes to the design.

   Tip

   In the Block Diagram window, notice the message stating that designer assistance is available, as shown in the following figure. When designer assistance is available, you can click the link to have Vivado perform that step in your design.

   

3. You will now use a preset template created for the ZCU102 board. Click the Run Block Automation link.

   The Run Block Automation view opens.

4. Click OK to accept the default processor system options and make default pin connections.

   This configuration wizard enables many peripherals in the Processing System with some multiplexed I/O (MIO) pins assigned to them according to the board layout of the ZCU102 board. For example, UART0 and UART1 are enabled. The UART signals are connected to a USB-UART connector through UART to the USB converter chip on the ZCU102 board.

5. To verify, double-click the Zynq UltraScale+ Processing System block in the block diagram window.

   Note the check marks that appear next to each peripheral name in the Zynq UltraScale+ device block diagram, signifying the I/O Peripherals that are active.

   

6. In the block diagram, click one of the green I/O peripherals, as shown in the previous figure. The I/O Configuration view opens for the selected peripheral.

   

   This page enables you to configure low speed and high speed peripherals. For this example, you will continue with the basic connection enabled using Board preset for ZCU102.

7. In the Page Navigator, select PS-PL Configuration.

8. In PS-PL Configuration, expand PS-PL Interfaces and expand the Master Interface.

   The PS-PL AXI Master interface enables AXI HPM0 FPD and AXI HPM1 FPD in the default board setup. For this example, you start with a design with only PS logic (no PL), so the PS-PL interfaces can be disabled.

9. Deselect AXI HPM0 FPD and AXI HPM1 FPD. The PS-PL configuration looks like the following figure.

   

10. Click OK to close the Re-customize IP wizard.