Check and select the RPU Cortex-R5F Core 0 target ID.
xsct% targets xsct% targets -set -filter {name =~ "Cortex-R5 #0"} xsct% rst -processor
The command
rst -processorclears the reset on an individual processor core.This step is important, because when the Zynq MPSoC boots up JTAG boot mode, all the Cortex-A53 and Cortex-R5F cores are held in reset. You must clear the resets on each core before debugging on these cores. The
rstcommand in XSDB can be used to clear the resets.Note
The command rst -cores clears resets on all the processor cores in the group (such as APU or RPU), of which the current target is a child. For example, when A53 #0 is the current target, rst - cores clears resets on all the Cortex-A53 cores in the APU.
Download the testapp_r5 application on Arm Cortex-R5F Core 0.
Run xsct% dow {C:edttestapp_r5Debugtestapp_r5.elf} or xsct% dow {C:/edt/testapp_r5/Debug/testapp_r5.elf}.
At this point, you can see the sections from the ELF file downloaded sequentially. The XSCT prompt can be seen after successful download. Now, configure a serial terminal (Tera Term, Minicom, or the serial terminal interface for a UART-1 USB-serial connection).