Loading U-Boot Using XSCT/XSDB - 2024.2 English - UG1209

Download the U-Boot application on Cortex-A53 #0 using the following commands.

1. By default, JTAG security gates are enabled. Disable the security gates for DAP, PL TAP, and PMU (this makes the PMU MB target visible to the debugger).

   xsct% targets -set -filter {name =~ "PSU"}
   xsct% mwr 0xffca0038 0x1ff
   xsct% targets
   

2. Verify if the PMU MB target is listed under the PMU device. Now, load and run the PMU firmware.

3. Reset APU Cortex-A53 Core 0 to load and run FSBL.

   xsct% targets -set -filter {name =~ "Cortex-A53 #0"}
   xsct% rst -processor
   

   Note

   rst -processor clears the reset on an individual processor core.

   This step is important, because when the Zynq UltraScale+ MPSoC boots up in JTAG boot mode, all the APU and RPU cores are held in reset. You must clear the resets on each core before performing debugging on these cores. You can use the rst command in XSCT to clear the resets.

   Note

   The rst -cores command clears the resets on all the processor cores in the group (that is, the APU or RPU) of which the current target is a child. For example, when A53 #0 is the current target, rst -cores clears resets on all the Cortex-A53 cores in the APU.

4. Load and run FSBL.

   xsct% dow {C:\edt\fsbl_a53\Debug\fsbl_a53.elf}
   xsct% con
   

5. Verify the FSBL messages on the Serial Terminal and stop FSBL after a couple of seconds.

   xsct% stop
   

6. Load and run the TF-A.

   xsct% dow {C:\edt\qspi_boot\bl31.elf}
   xsct% con
   xsct% stop
   

Configure a Serial Terminal (Tera Term, Minicom, or the Serial Terminal interface for a UART-0 USB-serial connection).

For Serial Terminal settings, see the following figure.

Load and run U-Boot.

xsct% dow {C:\edt\qspi_boot\u-boot.elf}

Run U-Boot, using the con command in XSDB.

xsct% con

In the target Serial Terminal, press any key to stop the U-Boot auto-boot.

Stop the core using the stop command in XSDB.

xsct% stop