Design Input and Output files - 2024.2 English - UG1209

Zynq UltraScale+ MPSoC Embedded Design Tutorial (UG1209)

Document ID
UG1209
Release Date
2025-01-07
Version
2024.2 English

This example design requires no input files. We will create the Vivado design from scratch. The design includes the processing system module of the MPSoC. No PL IPs will be added in this example design, so this design does not need to run through implementation and bitstream generation.

The output of this example design is the hardware configuration XSA. It will be used for further software development.

  • Input: N/A

  • Output: edt_zcu102_wrapper.xsa