Creating the Bare-Metal Application Project - 2024.2 English - UG1209

Zynq UltraScale+ MPSoC Embedded Design Tutorial (UG1209)

Document ID
UG1209
Release Date
2025-01-07
Version
2024.2 English
  1. Launch Vitis and use a new workspace: \edt\design\_example_1*\* for this project.

  2. In the Vitis IDE, select File → New → Application Project. The New Project wizard opens.

  3. Use the information in the table below to make your selections in the wizard.

    Screen

    System Properties

    Settings

    Platform

    Create a New Platform from Hardware

    edt_zcu102_wrapper.xsa

    Generate Boot Components

    uncheck

    Application Project Details

    Application project name

    tmr_psled_r5

    System project name

    tmr_psled_r5_system

    Target processor

    psu_cortexr5_0

    Domain

    Domain

    psu_cortexr5_0

    Templates

    Available templates

    Empty Application(C)

  4. Click Finish.

    The New Project wizard closes and the Vitis IDE creates the tmr_psled_r5 application project, which you can view in the Project Explorer.

  5. In the Project Explorer tab, expand the tmr_psled_r5 project.

  6. Right-click the src directory, and select Import to open the Import dialog box.

  7. Expand General in the Import dialog box and select File System.

  8. Click Next.

  9. Select Browse and navigate to the ref_files/design1 folder.

  10. Click OK.

  11. Select and add the timer_psled_r5.c file.

  12. Click Finish.

The Vitis IDE automatically builds the application and displays the status in the console window.