Configuring Hardware - 2024.2 English - UG1209

Zynq UltraScale+ MPSoC Embedded Design Tutorial (UG1209)

Document ID
UG1209
Release Date
2025-03-20
Version
2024.2 English

The first step in this design is to configure the PS and PL sections. This can be done in Vivado IP integrator. Start with adding the required IPs from the Vivado IP catalog, and then connect the components to blocks in the PS subsystem.

  1. If the Vivado Design Suite is already open, start from the block diagram shown in and jump to step 4.

  2. Open the Vivado project that you created in the introduction tutorial:

    C:/edt/edt_zcu102/edt_zcu102.xpr

  3. Save the project as design_example_1:

    1. Click File → Project → Save As.

    2. Input project name design_example_1.

    3. Deselect Include run results.

    4. Click OK.

    _images/vivado_save_project_as.png
  4. In the Flow Navigator, under IP integrator, click Open Block Design and select edt_zcu102.bd.

    _images/image96.png