Zynq UltraScale+ MPSoC Embedded Design Tutorial - 2024.1 English

Document ID: UG1209
Release Date: 2024-09-12
Version: 2024.1 English

Zynq UltraScale+ MPSoC Embedded Design Tutorial
Zynq UltraScale+ MPSoC Embedded Design Tutorial
How Zynq UltraScale+ Devices Offer a Single Chip Solution
Vitis Integrated Design Environment
Vivado Design Suite
PetaLinux Tools
How the Xilinx Design Tools Expedite the Design
Getting Started
Hardware Requirements
Installation Requirements
Vitis Integrated Design Environment and Vivado Design Suite
PetaLinux Tools
Tutorial Design Files
Next Chapter
Zynq UltraScale+ MPSoC Processing System Configuration with the Vivado Design Suite
Zynq UltraScale+ System Configuration
Example 1: Creating a New Embedded Project with Zynq UltraScale+ MPSoC
Design Input and Output files
Starting Your Design
Creating a Block Design Project
Managing the Zynq UltraScale+ Processing System in Vivado
Validating the Design, Creating the Wrapper, and Generating the Block Design
Exporting Hardware
Example Summary
Building Standalone Software for PS Subsystems
Example 2: Creating a Platform Project Using Vitis IDE
Example Input and Output Files
Creating the Platform Project
Example 3: Running the “Hello World” Application from Arm Cortex-A53
Input and Output Files
Board Setup
Connecting the Serial Port
Creating a Hello World Application on Arm Cortex-A53
Running Hello World on the Board
What Just Happened?
One Step Further
Additional Information
Domain
Board Support Package
Standalone BSP
Example 4: Running the “Hello World” Application from Arm Cortex-R5
Input and Output Files
Creating a Standalone BSP Domain for cortexr5_0
What Just Happened?
Creating a “Hello World” Application on Arm Cortex-R5F
Running the “Hello World” Application on Arm Cortex-R5F
Example 5: Using System Project to Manage Multiple Applications in the Vitis IDE
Input and Output Files
Creating the hello_system System Project
Modifying the hello_sys_a53 Application Source Code
Creating a Custom Bare-Metal Application for an Arm Cortex-R5F Based RPU in the Same System Project
Modifying the Linker Script for testapp_r5
Modifying the Board Support Package for testapp_r5
Running the hello_system System Project on Hardware
What Just Happened?
Reviewing Bootloader Projects in the Platform
Reviewing FSBL in the Platform
Reviewing the PMU Firmware in the Platform
Debugging Standalone Applications with the Vitis Debugger
Xilinx System Debugger
Example 6: Debugging Software Using the Vitis Debugger
Example 7: Debugging Using XSCT
Setting Up the Target
Loading the Application Using XSCT
Serial Terminal Configuration
Running and Debugging the Application Using XSCT
Building and Debugging Linux Applications
Example 8: Creating Linux Images and Applications using PetaLinux
Input and Output Files
Creating a PetaLinux Image
Verifying the Image on the ZCU102 Board
Creating Linux Applications in the Vitis IDE
Preparing the Linux Agent for Remote Connection
Running the Linux Application from the Vitis IDE
Debugging a Linux Application from the Vitis IDE
Summary
Design Example 1: Using GPIOs, Timers, and Interrupts
Configuring Hardware
Adding the AXI Timer and AXI GPIO IP
Connecting IP Blocks to Create a Complete System
Exporting the Post-Implementation Hardware Platform
Configuring Software
Configuring and Building Linux Using PetaLinux
Creating the Bare-Metal Application Project
Modifying the Linker Script
Creating the Linux Domain for Linux Applications
Creating the Linux Application Project
Modifying the Build Settings
Creating a Boot Image
Running the Image on a ZCU102 Board
Preparing the SD Card
Target Setup
Power On Target and Run Applications
Running Linux Applications
Reference Design Automation
Summary
Boot and Configuration
System Software
First Stage Boot Loader
Platform Management Unit Firmware (PMUFW)
U-Boot
Trusted Firmware-A (TF-A)
Linux on APU
Bare Metal on the RPU
Boot Sequence for SD-Boot
Running the Image on the ZCU102 Board
Boot Sequence for QSPI Boot Mode
Creating Linux Images Using PetaLinux for QSPI Flash
Boot Image Setup in Vitis
Running the Image in QSPI Boot Mode on ZCU102 Board
Setting Up the ZCU102 Board
Boot Sequence for QSPI-Boot Mode Using JTAG
Setting Up the Target
Loading U-Boot Using XSCT/XSDB
Load boot.bin in the DDR Memory Using XSDB
Loading the boot.bin Image in QSPI Using U-Boot
Boot Sequence for USB Boot Mode
Configuring FSBL to Enable USB Boot Mode
Create First Stage Boot Loader for USB Boot
Creating Boot Images for USB Boot
Modifying PetaLinux U-Boot
Boot Using USB Boot
Boot Commands for Linux Host Machine
Boot Commands for Windows Host Machine
Use Secure Boot Features to Protect Your Design
Secure Boot System Design Decisions
Hardware Root of Trust
Data Integrity
Authentication
Boot Image Confidentiality and DPA
DPA Protections
Black Key Storage
Example: Practical Methods in Secure Boot
Sample Design Overview
Generating Keys for Authentication
Creating RSA Private/Public Key Pairs
Generating SHA3 of Public Key in an RSA Private/Public Key Pair
Additional RSA Private/Public Key Pairs
Enabling Boot Header Authentication
Generating Keys for Confidentiality
Using AES Encryption
Enabling DPA Protections
Enabling Use of an Operational Key
Enabling Encryption Using Key Rolling
Generating All of the AES Keys
Using Key Revocation
Using the PUF
PUF Registration in Boot Header Mode
Using PUF in Boot Header Mode
System Example Using the Vitis IDE Create Boot Image Wizard
Booting the System Using a Secure Boot Image
Running the Linux Application
Sample BIF for a Fielded System
Debugging Problems with Secure Boot
Determine if PUF Registration is Running
Read the Boot Image

Back to home page