Phase 1: XSA to SDT Generation - Phase 1: XSA to SDT Generation - 2026.1 English - UG1186

Prerequisites

You need the following input files and tools before you generate the SDT.

• Input file: Start with a hardware design that Vivado exports as <design_name>.xsa. For VEK385, this file typically includes the Versal2 device configuration, peripherals, and memory mappings. Also use the domain YAML file, meta-xilinx/meta-xilinx-standalone-sdt/conf/domainyaml/openamp-overlay-versal-2ve-2vm.yaml at rel-v2025.2 · Xilinx/meta-xilinx.
• Tool required: Use sdtgen, which is the SDT generation tool from AMD. This tool is part of the embedded software tools suite that is typically in AMD Vitis™ or PetaLinux installations.

SDT Generation Command

Use the following command to generate the SDT:

sdtgen \
  -xsa <path-to-xsa>/<design_name>.xsa \
  -out <output-directory> \
  -dtsi <system-top.dtsi>

The following example shows this command for the VEK385 platform:

sdtgen \
  -xsa hw/versal-2ve-2vm-vek385-revb.xsa \
  -out build/hw-description/versal-2ve-2vm-vek385-revb-sdt-seg \
  -dtsi system-top.dtsi

SDT Output Structure

After you run sdtgen, the output directory contains the generated SDT files.

versal-2ve-2vm-vek385-revb-sdt-seg/
├── system-top.dts           # Main system device tree
├── system-top.dtsi          # device tree include with hardware nodes
├── pl.dtsi                  # Programmable Logic devices, if present
├── versal-net.dtsi          # Versal2 SoC base definitions

The key file is system-top.dts. This file is the unpruned, complete system device tree. It describes all hardware in the design.

SDT Content Overview

The generated system-top.dts includes the following:

• CPU nodes: APU (Cortex-A78), RPU (Cortex-R52), PMC, PSM
• Memory nodes: DDR, OCM, TCMs (ATCM, BTCM, CTCM)
• Peripheral nodes: UART, I2C, SPI, CAN, Ethernet, etc.
• Interrupt controllers: GIC for APU, R5 GIC, IPI mailboxes
• Clock and reset nodes: Clock tree, reset controllers
• Power domains: PM subsystem nodes