Validating the Design and Connecting Ports - 2023.2 English

Now, let’s validate the design.

1. Right-click in the white space of the Diagram window and select Validate Design. Alternatively, you can press the F6 key or the check button on the block diagram toolbar.

   • A critical message appears, indicating that the M_AXI_GP0_ACLK must be connected.

     

   • Click OK to close the message window.

2. Connect the M_AXI_GP0_ACLK signal to PS generated PL clock signal.

   • The PS can generate four clock signals with FCLK_CLK<number>. These are the clocks for the PL fabric. The clock frequency can be adjusted in PS block settings.

   • In the Diagram window of the ZYNQ7 Processing System block, locate the M_AXI_GP0_ACLK port. Hover your mouse over the connector port until the pencil button appears.

   • Click the M_AXI_GP0_ACLK port and drag to the FCLK_CLK0 port to make a connection between the two ports.

     

3. Validate the design again to ensure there are no other errors.

   • Right-click in the white space of the Diagram window and select Validate Design.

   A dialog box with the following message opens:

   Validation successful. There are no errors or critical warnings in this design.

   • Click OK to close the message.