Update the Vivado Design - 2023.2 English

Start with the system you created in Example 6: Adding Peripheral PL IP.

1. Open the Vivado® design from Example 6: Adding Peripheral PL IP.

2. Open the block design from Flow Navigator Open Block Design.

Add the CDMA IP:

1. In the Diagram window, right-click in the blank space and select Add IP.

2. In the search box, type “CDMA” and double-click the AXI Central Direct Memory Access IP to add it to the block design. The AXI Central Direct Memory Access IP block appears in the Diagram view.

Add the Contact IP to concatenate the interrupt signals:

1. In the Diagram window, right-click in the blank space and select Add IP.

2. In the search box type “concat” and double-click the Concat IP to add it to the block design. The Concat IP block appears in the Diagram window. This block is used to concatenate the two interrupt signals if you are using the prior design with the AXI Timer.

3. Right-click the net from the interrupt port to the IRQ_F2P[0:0] port and select Delete.

4. Click the IRQ_F2P[0:0] port and drag to the dout[1:0] output port on the Concat IP core to make a connection between the two ports.

5. Click the interrupt port on the AXI Timer IP core and drag to the In0[0:0] input port on the Concat IP core to make a connection between the two ports.

6. Click the cdma_introut port on the AXI CDMA IP core and drag to the In1[0:0] input port on the Concat IP core to make a connection between the two ports.

Customize the PS to enable the AXI HP0 and AXI HP2 interface:

1. Right-click the ZYNQ7 Processing System core and select Customize Block.

2. Select PS-PL Configuration and expand the HP Slave AXI Interface.

3. Select the checkbox for S AXI HP0 interface and for S AXI HP2 interface.

4. Click OK to accept the changes.

Customize the CDMA IP:

1. Right-click the AXI CDMA IP core and select Customize Block.

2. Set the block settings in the Re-customize IP wizard page as follows:

   System Property	Setting or Command to Use
   Enable Scatter Gather	Unchecked
   Disable 4K Boundary Checks	Unchecked
   Allow Unaligned Transfers	Unchecked
   Write/Read Data Width	1024
   Write/Read Burst Size	32
   Enable Asynchronous Mode (Auto)	Unchecked
   Enable CDMA Store and Forward	Unchecked
   Address Width	32

3. Click OK to accept the changes.

Connect the blocks

1. Click the Run Connection Automation link in the Diagram window to automate the remaining connections.

2. In the Run Connection Automation dialog box make sure the All Automation box is checked, then click OK to accept the default connections. The finished diagram should look like the following figure.

   

   Note

   You might receive a critical warning message regarding forcibly mapping a net into a conflicting address. Address the error by manually updating the memory mapped address in the next steps. Click OK if you see the error message.

Assign the address manually. In most cases, Vivado connection automation can set up the address correctly. In the current use case, it is confused by the physical connection because HP0 and HP2 now cover the same address range. Resolve this issue by making sure that the address range of these two ports does not overlap.

1. Select the Address Editor window.

   

2. In the Address Editor window, expand axi_cdma_0 → axi_cdma_0/Data. Right-click HP2_DDR_LOWOCM and select Unassign.

3. In the Range column for S_AXI_HP0, select 256M.

4. Under Offset Address for S_AXI_HP0, set a value of 0x2000_0000.

5. In the Address Editor window, expand axi_cdma_0 → axi_cdma_0/Data → Unassigned. Right-click HP2_DDR_LOWOCM and select Assign.

6. In the Range column for S_AXI_HP2, select 256M.

7. Under Offset Address for S_AXI_HP2, set a value of 0x3000_0000.

   

Generate the bitstream:

1. In the Flow Navigator, select Generate Bitstream under PROGRAM AND DEBUG. The Save Project dialog box opens.

2. Ensure that the Block Design - system check box is selected, then click Save.

   A message might appear that states synthesis is out of date. If it does, click Yes.

Export the hardware after bitstream generation completes by clicking File → Export → Export Hardware.