Update Vivado Design Diagram - 2023.2 English

In this example, you will add the AXI GPIO, AXI Timer, the interrupt instantiated in the fabric, and the EMIO interface. You will then validate the fabric additions.

1. Open the Vivado design created in Example 1: Creating a New Embedded Project with Zynq SoC:

   1. Launch the AMD Vivado™ IDE.

   2. Under the Recent Projects column, click the edt_zc702 design that you created in Example 1: Creating a New Embedded Project with Zynq SoC.

   3. In Flow Navigator window, click Open Block Design under IP Integrator.

2. Add the AXI GPIO and AXI Timer IP:

   1. In the Diagram window, right-click in the blank space and select Add IP.

   2. In the search box, type AXI GPIO and double-click the AXI GPIO IP to add it to the block design. The AXI GPIO IP block appears in the Diagram window.

   3. In the Diagram window, right-click in the blank space and select Add IP.

   4. In the search box, type AXI Timer and double-click the AXI Timer IP to add it to the block design. The AXI Timer IP block appears in the Diagram view.

3. Enable the ZYNQ7 Processing System EMIO GPIO:

   1. Double-click the ZYNQ7 Processing System IP block.

      The Re-customize IP dialog box opens, as shown in the following figure.

      

      Recustomize ZYNQ7 PS 5.5

   2. Click MIO Configuration.

   3. Expand I/O Peripherals→ GPIO and enable the EMIO GPIO (Width) check box.

   4. Change the EMIO GPIO (Width) to 1.

4. Enable the ZYNQ7 Processing System interrupt:

   1. Navigate to Interrupts → Fabric Interrupts → PL-PS Interrupt Ports.

   2. Check the Fabric Interrupts box to enable PL to PS interrupts.

   3. Check IRQ_F2P[15:0] to enable general interrupts. The CoreN_nFIQ signals are used for fast interrupt.

   4. Click OK to accept the changes to the ZYNQ7 Processing System IP. The diagram looks like the following figure.

      

      BD with Timer and GPIO

5. Connect the PL IPs:

   1. Click the Run Connection Automation link at the top of the page to automate the connection process for the newly added IP blocks.

   2. In the Run Connection Automation dialog box, select the check box next to All Automation, as shown in the following figure.

      

      Connection Automation

   3. Click OK.

      Upon completion, the updated diagram looks like the following figure.

      

      Connected

6. Customize the AXI GPIO IP block:

   1. Double-click the AXI GPIO IP block to customize it.

   2. Under the Board page, make sure that both GPIO and GPIO2 are set to Custom.

   3. Select the IP Configuration page. In the GPIO section, change the GPIO Width to 1 because you only need one GPIO port.

   4. Ensure that All Inputs and All Outputs are both unchecked.

   5. Click OK to accept the changes.

7. Connect interrupt signals:

   • Notice that the Interrupt port is not automatically connected to the AXI Timer IP Core. In the Block Diagram view, locate the IRQ_F2P[0:0] port on the ZYNQ7 Processing System.

   • Scroll your mouse over the connector port until the pencil button appears, then click the IRQ_F2P[0:0] port and drag to the interrupt output port on the axi_timer_0 to make a connection between the two ports.

8. Make the PS GPIO port external:

   • Notice that the ZYNQ7 Processing System GPIO_0 port is not connected. Right-click the GPIO_0 output port on the ZYNQ7 Processing System and select Make External.

   The pins are external but do not have the required constraints for our board. To constrain your hardware pins to specific device locations, follow the steps below. These steps can be used for any manual pin placements.