Integrating Peripheral IP with PS GP Master Port - 2023.2 English

Zynq-7000 SoC Embedded Design Tutorial (UG1165)

Document ID
UG1165
Release Date
2024-05-02
Version
2023.2 English

You will now create a system for the ZC702 board by instantiating the peripheral IP as a slave in the Zynq SoC programmable logic (PL) section. You will then connect it with the processor through the processing system (PS) general purpose (GP) master port. The block diagram for the system is shown in the following figure.

../_images/image97.jpeg

This system covers the following connections:

  • Peripheral IP connected to PS general purpose master port 0 (M_AXI_GP0). This connection is used by the PS CPU to configure peripheral IP register configurations.

  • Four output ports for peripheral IP connected to DS15, DS16, DS17, and DS18 on-board LEDs.

In this system, when you run application code, a message appears on the serial terminal and asks you to choose the option to make the LEDs start or stop blinking.

  • When you select the start option on the serial terminal, all four LEDs start blinking.

  • When you select the stop option, all four LEDs stop blinking and retain the previous state.