Two types of hardware can be exported from Vivado: pre-synthesis and post-implementation. In the block design for this example, the hardware in the PL is the signal from FCLK_CLK0
to M_AXI_GP0_ACLK
. It drives the clock of M_AXI_GP0
, because only pure PS functions will be tested in this example and PL resources will not be used, no loads are added to the M_AXI_GP0
AXI interface. You can skip the synthesis, implementation, and bitstream generation phases to save time. We will export the pre-synthesis hardware in this case.
From the Vivado main menu, select File→ Export → Export Hardware. The Export Hardware Platform wizard opens.
Use the information in the following table to make selections in each of the wizard screens. Click Next wherever necessary.
Screen
System Property
Setting or Command to Use
Output Files
XSA file name Export to
Pre-synthesis. Leave as system_wrapper. Leave as C:/edt/edt_zc702.
Click Finish.
After a while, the Vivado Tcl Console reports the following message;
system_wrapper.xsa
is the exported hardware handoff file.write_hw_platform -fixed -force -file C:/edt/edt_zc702/system_wrapper.xsa INFO: [Vivado 12-4895] Creating Hardware Platform: C:/edt/edt_zc702/system_wrapper.xsa ... INFO: [Hsi 55-2053] elapsed time for repository (C:/Xilinx/Vivado/2023.2/data/embeddedsw) loading 1 seconds INFO: [Vivado 12-12467] The Hardware Platform can be used for Hardware INFO: [Vivado 12-4896] Successfully created Hardware Platform: C:/edt/edt_zc702/system_wrapper.xsa