Creating an HDL Wrapper for the Block Diagram - 2023.2 English

Zynq-7000 SoC Embedded Design Tutorial (UG1165)
Document ID
UG1165
Release Date
2024-05-02
Version
2023.2 English

  1. Click the Sources window.

    It should be in the Hierarchy tab by default. If it is not there, click the Hierarchy tab.

  2. Expand Design Sources, right-click the block diagram file system(system.bd), and select Create HDL Wrapper.

    The Create HDL Wrapper view opens. You will use this view to create an HDL wrapper file for the processor subsystem.

    Tip

    The HDL wrapper is a top-level entity required by the design tools.

  3. Select Let Vivado manage wrapper and auto-update and click OK.

    system_wrapper.v is generated. It is set to the top module of this design automatically.